This example demonstrates UART communication using UART1. Interrupt conditions on the UART peripheral are handled, input is tested, output is produced, and upon receiving the 0 character, DMA-driven output is initiated.
The DMA-driven output demonstrates mechanisms employed by some of the VGA examples. A channel is enabled by the interrupt handler and its transfers each initiated by a timer; this should cause text to be transmitted relatively slowly across the serial connection...
When this first channel completes all transfers, two other channels chained to it are enabled. Another timer then causes their transfers to be initiated. Since these two channels effectively compete for access to the UART peripheral, their transfers are interleaved. Regardless of the configuration of the example, more text should be transmitted relatively slowly...
And once again, hello!
Although such DMA channel interleaving is rather exotic, other techniques employed by the example are likely to be applicable elsewhere.
The pin usage of this solution is documented below.
MCLR# 1 \/ 28 RA0 2 27 RA1 3 26 RB15/U1TX RB0 4 25 RB14 RB1 5 24 RB13/U1RX RB2 6 23 RB3 7 22 RB11/PGEC2 8 21 RB10/PGEC3 RA2 9 20 RA3 10 19 RB4 11 18 RB9 12 17 RB8 13 16 RB7 RB5 14 15
Note that RB6 is not available on pin 15 on this device (it is needed for VBUS unlike the MX170 variant).
UART1 is exposed by the RB13 and RB15 pins.